Brightiness control circuitry for direct view storage tubes



May 14, 1968 A. D. cHoPEY 3,383,546

BRIGHTNESS CONTROL CIRCUITRY FOR DIRECT VIEW STORAGE TUBES Filed Jan.l5, 1965 2 Sheets-Sheet l (Maman/way 26 2f; +V

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May 14, 1968 A. D. cHoPr-:Y 3,383,546

BRIGHTNESS CONTROL CIRCUITRY FOR DIRECT VIEW STORAGE TUBES /m/ @#45457my VIP/[P United States Patent Oiiice 3,383,546 Patented May 14, 19683,383,546 BRIGHTNESS CONTROL CIRCUITRY FOR DIRECT VIEW STORAGE TUBESAlbert D. Chopey, Glen Burnie, Md., assignor, by mesne assignments, tothe United States of America as represented by the Secretary of the NavyFiled Jan. 15, 1965, Ser. No. 425,976 4 Claims. (Cl. 315-12) ABSTRACT FTHE DISCLOSURE A brightness control circuit for direct view storagetubes having parallel channels, one channel to develop erase pulses forthe backing electrode of the storage tube and the other channel todevelop brightness pulses, coincident in initial time and longer induration than the erase pulses, for the suppressor grid of the storagetube to minimize the flashing etects of the erase pulses. The twochannels have a common triggering pulse source and the channeldeveloping the brightness pulse has a brightness pulse generator, theoutput of which is through an OR gate, together with the erase pulses,and through a brightness pulse amplier to the suppressor grid to insurebrightness pulse application although a brightness pulse fails todevelop in its channel.

Background of the invention This invention relates to circuitry forcontrolling display intensity of direct view storage tubes (DVST) andmore particularly to circuitry for producing voltage pulses coincidentin time with erase pulses, and of opposite polarity and greaterdurationthan the erase pulses, for application to the suppressor grid of theDVST to minimize or eliminate the ashing effects of the erase pulses.

Recent development in the storage tube industry has led to the additionof a suppressor grid in some DVST models. This new grid is located inthe viewing or flooding gun system of the tube and is placed between thebacking electrode to which the erase pulses are applied and thephosphorescent screen. By varying the direct current (D.C.) voltageapplied to this suppressor grid, it is possible to control the ow ofelectrons striking the screen or the display of target information wherethe DVST is used in a radar system. The intensity or brightness of thedisplay can -be controlled by applying pulses to the suppressor grid andvarying their duty cycle.

Operation of any DVST requires pulsing the backing electrode with erasepulses. These pulses erase stored infomation in the form of charges onthe storage surface adjacent to the backing electrode. Here again, dutycycle variation is used and determines display persistence. Erase pulsesare normally in the form of posi-tive pulses. Through electrostaticcharging these pulses result in the addition of electrons to the storagesurface which in turn nullify positively charged areas of informationpreviously written by the DVST writing guns. In DVSTS, which do notcontain a suppressor grid, or which do contain suppressor grids of xedbias, this positive pulsing of the backing electrode causes bursts ofelectrons to hit the phosphorescent screen. The result is a ashingdisplay. Due to the duty cycle and frequency of the erase pulses theflashing manifests itself in a display with a bright background sincethe eye cannot resolve the individual ilashes but rather averages theoverall intensity level. Taking advantage of the suppressor grid in thenewer DVST models and pulsing the suppressor grid in proper phaserelation with the backing electrode by erase pulses, this ashing displaycan be minimized or controlled.

Summary of the invention In the present invention the pulse source whichproduces the erase pulses on the backing electrode of the DVST isutilized in a second channel for developing a brightness pulsecoincident in time with the leading edge of the erase pulse but oppositein polarity and of equal or greater pulse width for application to thesuppressor grid of the DVST. The erase pulses are ordinarily generatedby an astable multivibrator having an adjustable pulse width controlmeans therein to vary the `duty cycle of the pulses which will controlthe DVST persistence on the display screen. This same Iastablemultivibrator pulse source is applied to a monostable multivibratorha'ving adjustable means therein to vary the duty cycle of the outputbrightness pulses produced thereby which will control the brightness ofthe DVST liuorescent screen upon the application of these pulses to thesuppressor grid. The erase pulses and brightness pulses are coupled tothe suppressor grid through an OR gate so that a brightness pulse willbe applied to the suppressor grid even though the brightness monostablemultivibrator fails to produce a brightness pulse. In both channels ofthe erase pulses and the brightness pulses, biasing circuitry isprovided and inverters are provided, where necessary, to produce thebrightness pulse on the suppressor grid 'of the DVST in an oppositepolarity or phase relation with Brief description of the drawing Theseand other objects and the attendant advantages, features, and uses ofthis invention will become more apparent to those skilled in the art asa more detailed description proceeds herein taken in conjunction withthe accompanying drawings, in which:

FIGURE 1 is a simplified illustration of the gun, grids, and fluorescentscreen of a DVST having a suppressor grid;

FIGURE 2 is a block schematic diagram of one embodiment of theinvention;

FIGURE 3 is a block schematic diagram of a second embodiment of theinvention;

FIGURE 4 is a block schematic and partially circuit schematic of a thirdembodiment of the invention; and

FIGURE 5 is a circuit schematic of the embodiment shown in FIGURE 4.

Description of the preferred embodiments Referring more particularly toFIGURE 1 where a simplified illustration is shown of a DVST, the gunportion is illustrated only by the cathode 10 producing viewing gunelectron beams 11 toward a collector 12, a storage surface 13, a backingelectrode 14, a suppressor grid 15, and a phosphorescent screen 16. Aswell understood by those skilled in the art of DVSTs, the erase pulsesare applied to the backing electrode, herein shown as being applied bythe conductor means 17. In accordance with this invention, brightnesspulses are used to eliminate the ashing effects on the fluorescentscreen 16 caused by the application of erase pulses over conductor means17. These brightness pulses are applied to the suppressor grid by Way ofthe conductor Ameans 18. The application of negative voltage 4brightnesspulses by way of conductor 18, as will be disclosed below, willcompensate for the positive voltage erase pulses applied by Way ofconductor means 17.

Referring more particularly to FIGURE 2, there is illustrated in blockcircuit schematic one means of developing negative voltage brightnesspulses for the suppressor grid coincident with positive erase pulses forapplication to the backing electrode of the DVST shown in FIG- URE 1. Inthis embodiment erase pulses are produced by an astable multivibrator 2@having variable resistance adjustable means 21 for varying the trailingedge of an output pulse identified by pulse A With trailing edge t1 at avoltage level V1 fixed by the bias of resistor 22. The erase pulse Awill be conducted by the conductor means 17 to the backing electrode 14of the DVST. This erase pulse A is likewise conducted by means ofconductor 23 to a monostable multivibrator 24, referred to herein and inthe drawings as .the brightness multivibrator. The brightnessmultivibrator 24 has a variable resistance lmeans 25 as a brightnesscontrol which varies the pulse width or the trailing edge, identified ast2 of the generated pulse B on the Output thereof, and a fixed resistor26 provides the bias on the output pulse, identified in FIGURE 2 as V1voltage, corresponding to the voltage bias by the resistor 22 for theerase multivibrator 213. The output pulses B of the brightnessmultivibrator 24 are conducted by Way of the output conductor 27 to anOR gate 2S to which is also applied the erase pulses by way of thebranch conductor 23 and a branch conductor 29. The output of the OR gate2S is applied by way of conductor means 36 to a brightness amplifiertube circuit 31 to produce the amplified brightness pulses C on theoutput conductor 13 which is coupled to the suppressor grid 15 of theDVST. The brightness amplifier tube circuit 31 has biasing voltagesapplied at terminals 32 and 33 to establish the -l-VZ voltage on theoutput pulse C. A tube is used in the brightness amplifier 31 to isolatethe above-described circuitry from any arcs which may occur within theDVST thereby protecting this circuitry, which is preferably circuitryutilizing transistors to provide a compact and light weight package.

In the operation of FIGURE 1, the generation of erase pulses A by theastable multivibrator 20 will cause the brightness multivibrator 24 togenerate similar pulses B for the suppressor grid 15 of the DVST. Sincethe brightness multivibrator 24 is triggered by the leading edge of theerase pulses A from the erase multivibrator 20, the erase pulses A andbrightness pulses C are coincident in time, represented by to, forapplication to the backing electrode and suppressor grid, respectively.The control means 21 and 25 are adjustable to control the pulse Width ofA and the pulse width of C and, consequently, their duty cycles. Thepulse width of C should always be at a time t1 or greater, herein shownto be t2, to fully compensate or eliminate flashing of the DVSTiiuorescent screen by the erase pulses A.

Referring more particularly to FIGURE 3, an astable multivibrator orother equivalent clock pulse source 35 produces pulses D in common to anerase monostable multivibrator 36 and a brightness monostablemultivibrator 37 in each of two channels to the backing electrode 14 andsuppressor grid 15 of the DVST by way of conductor means 17 and 18,respectively. The erase pulse multivibrator 36 has a persistencevariable rresistance control means 38 while the brightness multivibrator37 has a brightness varia-ble resistor control means 39. The erasemultivibrator 36 utilizes the leading edge to of the clock pulse D togenerate the erase pulse E on its output conductor 40. Conductor 40' hasa biasing circuit network 41 coupled thereto from a positive voltagesource 42 and ground to bias the erase pulse F on the output conductor17 at a voltage V1. The brightness multivibrator 37 produces thebrightness pulse G on the output conductor 43 which is applied t an ORgate 44 together with the erase pulse E by way of the branch conductor45 from the erase multivibrator 36. Here again, as in FIGURE 2,

the OR gate 44 insures that a brightness pulse will exist at all timesthat an erase pulse is generated. T he brightness pulse G is conductedthrough the OR gate 44 over the output conductor 46 through a brightnessamplifier tube circuit Li7 which includes bias networks from thepositive voltage source 48 and the negative voltage source i9 toestablish the brightness pulse H over the output conductor 18 at thedesired voltage level V2. In like manner, the erase pulse F and thebrightness pulse H will `be conducted respectively over the outputconductors 17 and 18 to the backing electrode 14 and suppressor grid 15,respectively, as in the case of the operation of FIG- URE 2. As inFIGURE 1, the time duration of the brightness pulse H, to to t2, shouldnever be less than the time interval of the erase pulse F from to to t1to eliminate the flashing effects caused by the erase pulse in the DVST.Since the adjusting means 38 is capable of adjusting the time I0 to t1for the erase pulse F, or tube persistence on the screen of the DVST,and since the brightness on the screen 16 of the DVST iS adjustable bythe control means 39 to adjust the time interval to to t2 on thebrightness pulse H, these two adjustments 38 and 39 are variable toobtain the optimum persistence and brightness results from the DVSTshown in FIGURE 1.

Referring more particularly to FIGURE 4 where like reference charactersrefer to like parts in other figures, the astable multivibrator or clockpulse source 35 applies pulses to the erase multivibrator 36 to generatethe erase pulses E over the output conductor 40 and through biasingcircuitry 41 to establish the erase pulses F at the desired voltagelevel V1 in the same manner as shown in FIGURE 3. In this embodiment theclock pulses D also will be applied to a spike generator 50 having abrightness control 51 connected therewith to produce spike voltages Iwhich is varied in amplitude AV by the brightness control 51. The outputof the spike generator 50 is applied over the conductor means 52 througha diode 53 to a terminal 54 to which is coupled a resistor 55 in seriesto a negative voltage source 56. Terminal 54 is also coupled to oneplate of capacitor 57, the opposite plate of which is grounded. Thenetwork including the resistor 55 and capacitor 57 constitutes acharging network which stretches the spike J in time t0 to t2proportional to the amplitude of AV voltage. This stretched voltagewaveform K, is conducted through a diode 58 to a differentiating network59 which produces a square wave L on its output coextensive with At orin time relation ro to f2 corresponding with that of the Waveform K. Thedifferentiating output 59 is coupled through an inverter 60 to an ORgate 61 by the conductor means 62, a second input to the OR gate -61being the erase pulse E over the conductor 63 from the erasemultivibrator 36. Here again the OR gate 611 is used to insure that abrightness pulse will pass to the output 64 whenever an erase pulse E isgenerated. The brightness pulse L is applied to a brightness amplifiertube circuit and biasing network 65 to produce on its output 18 thebrightness pulse M at the desired voltage level V2. As in the priorFIGURES 2 and 3, the erase pulse F and brightness pulse M are generatedand applied to the backing electrode 14 and suppressor grid 15,respectively, of the DVST of a pulse width and bias to minimize oreliminate fiashing on the fiuorescent screen 16 normally caused by theerase pulses. If it is desirable to change the duty cycle of the erasepulse F, it is only necessary to adjust the persistence control 38,whereas, if it is necessary tochange the duty cycle of the brightnesspulse M, it is only necessary to adjust the brightness control 51. Thebrightness control 51 varies the AV amplitude which would vary Az in thewaveform K and thus control time t2 of the brightness of pulses L and M.As stated hereinbefore, the pulse vwidth to to t2 of the brightnesspulse M should always be equal to tu to t1 or greater for good resultsof eliminating flashing on the fluorescent screen 16 of the DVST by theerase pulse F.

Referring more particularly to FIGURE 5, which illustrates a preferredcircuit schematic diagram of the block circuit shown in FIGURE 4, theclock pulse multivibrator 35 is herein illustrated as being an astablemultivibrator utilizing two transistors, as Well understood by thoseskilled in the art and, accordingly, will not be eX- plained ordescribed in detail. The clock pulses D are applied through a couplingcapacitor 70 and a diode 71 to the erase multivibrator 36. Themultivibrator 36 is monostable, its stable condition being while theright transistor is conducting to produce a zero voltage on the outputconductor 63. When the negative clock pulse D is applied to themultivibrator 36, this negative clock pulse on the base of the righttransistor renders it nonconductive and the left transistor conductiveto produce a negative erase pulse E on the output 40 and a positiveerase pulse E on the output 63. The duration of the erase pulse E isdetermined by the adjustment on the persistence control means 38 to varythe RC constant for recovery of the monostable multivibrator 36 from acondition of left transistor conduction back to right transistorconduction, as well understood by those skilled in the multivibratorart. The output from the collector of the left erase multivibratortransistor is a negative pulse that is conducted through the diodes 72and 73 to the base of a transistor 74 which inverts the negative pulseto that of the erase pulse F, shown in FIGURE 4. The collector output isapplied through a Zener diode 75 to the adjustable tap of apotentiometer 76 having the resistance element in series with resistors77 and 78 from a positive voltage source 79 and ground. Input biasestablished on the base of transistor 74 is established by the resistors80 and 81. The Zener diode 75 etablishes the V1 voltage level for theerase pulse F. The output conductor 17 is coupled directly to thelmovable tap of potentiometer 76.

Clock pulses D are al-so applied through a coupling capacit-or 85 and adiode 86 to the base of a transistor 87 in the spike generator 50. Thebiases on the anode of the diode 86 and .the base of transistor 87 areestablished by a resistor 88 from -a voltage source 89 and by a resistor90 coupled to ground. The collector of the transistor 87 is coupled tothe adjustable tap of the potentiometer brightness control 51, theresistance element of which is coupled between a positive voltage sourceand ground. The brightness control adjustable tap is coupled directly tothe-base of a transistor 91 having its collector coupled directly to apositive voltage source and its emitter coupled through an emitter loadresistor 92 to ground. The coupling capacitor 85 and biasing resistor 88coupled to the diode 86 render only the leading edge of the clock pulsesD effective to produce the spike voltage I which reaches an -amplitudedirectly proportional to the brightness control 51 voltage setting. Thisspike voltage J is taken from the emitter of transistor 91 and appliedthrough the diode 53 to the terminal 54 in the network 55, 57 to producea sawtooth voltage K proportional to the amplitude of the spike voltageI. This sawtooth voltage K is applied through the diode 58 to the baseof a transistor 93 operating as a differentiating network by the biasthereon from resistors 94 and 95 and the ground on the emitter terminal.The collector produces the pulse L over conductor 59 which is applieddirectly to the base of a transistor 96 which inverts the pulse L on itscollector output 62. The positive pulse L on the inverter output 62 isapplied to the OR gate consisting of diodes 97 and 98, the output 62being through diode 97, while the output 63 from the erase multivibrator36 is through the diode 98. The output 64 of the OR gate is applieddirectly to the base of transistor 99 having its collector coupleddirectly to a positive voltage source and its emitter coupled through adiode 100 to ground. The emitter is also coupled through a Zener diode101 to the base of a transistor 102 having its collector coupled througha load resistor 103 to a positive voltage source and its emitter coupledthrough a voltage divider consisting of resistors 104 and 105 in seriesbetween a negative voltage source 106 and ground. The base of transistor102 is -biased from negative source 106 through a resistor 107. Thetransistor 102 operates as an inver-ter for the positive brightnesspulse L conducted from the emitter of transistor 99 to the base oftransistor 102 and taken from the collector of transistor 102. Thecollector of transistor 102 is coupled directly to the grid of a triodevacuum tube 108 having its anode coupled directly to a positive voltagesource and its cathode coupled through a resistor 109 to a negativeVoltage source. The output conductor 18 for the brightness pulse iscoupled directly to the cathode of the vacuum tube 108 operating as acathode follower isolating any transient voltages on the output 18 whichmay attempt to feed back into the transistor circuitry from the DVST.The Zener diode 101 and the negative bias on the cathode of tube 108through the -resistor 109 establish the voltage bias level on thebrightness pulse for application to the suppress-or grid 15 of the DVST.Since the operation of the circuit of FIGURE 5 in conjunction with theoperation explained f-or FIGURE 4 should be clear from the tracing ofthe various waveforms J, K, L, and M, through the circuitry, it isbelieved -that further discussion and description of the operation isunnecessary. As may be seen from the circuitry of the preferredillustrated form of the invention in FIGURE 5 for the 'block circuitdiagram in FIGURE 4, the erase and -brightness pulses connecte-d overthe outputs 17 and 18, respectively, to the b-acking electrode 14 andsuppressor grid 15 of the DVST will substantially eliminate or greatlyminimize flashing on the fluorescent screen 16 of the DVST normallyproduced by era-se pulses.

The embodiment sh-own in FIGURES 2 and 3 have a min-or disadvantage ofnot being able to generate a brightness pulse with a percent duty cycledue to the recovery -time characteristics of lthe mu-ltivibrators. Thereis no such disadvantage in the embodiment shown in FIGURE 4 since thevariable amplitude spike voltage generator triggered by the clock pulsecircuit and the RC charging network to generate a sawtooth wave shape don-ot have the recovery time ldilculties of multivibrator-s. Accordingly,it is possible to get Ia 100 percent duty cycle by generating a largepositive spike or high amplitude spike voltage I in the circuit ofFIGURES 4 and 5. When the circuits of FIGURES 4 and 5 Iare operate-dwith 100 percent duty cycle brightness pulses, the DVST flooding gun ofFIGUR-E Il is essentially turned off and a black background displayresults with only writing gun writingthrough being displayed.

While many modifications and changes may be made in the constructionaldetails and features of this invention witho-ut departing from thespirit and .scope of this invention for the intended purpose, it is tobe understood that I desire to be limited only by the scope of theappended claims.

I claim:

1. IIn a direct view storage tube having a backing electrode and asuppressor g-rid, a control circuit for coupling to the backingelectrode and suppressor grid thereof comprising:

generating means for generating voltage pulses over each of two channelsin leading edge time coincidence;

rst means in one said channel for developing each pulse .in one polaritywith adjustable means in said first means to vary pul-se width toproduce an erase pulse on an output thereof for application to the`backing electrode of the direct view storage tube;

a second means in said other channel for developing each pulse in theopposite polarity to said erase pulse with adjustable means in saidsecond means to vary pulse width to produce a brightness pul-se ofgreater pulse width than said erase pulse on an out-put thereof;

an OR gate coupled `to the outputs of said means of each channel to gateeither said erase pulse and brightness pulse on an output thereof; and

a brightness amplifier coupled to the output of said OR gate and havingan output for coupling to the Asuppressor grid of the direct Viewstorage tube where-by the brightn-ess of the direct view storage tube,with the control circuit coupled thereto, can be controlled upon theapplication of erase pulses.

2. Control circuitry for coupling to the backing elec- 10 trode andsuppressor grid of a direct view storage tube trode and the suppressorgrid of a direct view storage tube having backing and suppressor gridelectrodes comprising:

having backing and suppressor grid electrodes comprising:

a generator of xed frequency pulses conducted over :an astablemultivibrator adjustable to produce erase brightness pulse produced bythe triggering fixed frequency pulses; an OR gate coupled to the outputsof said first and two output channels;

pulses of variable width and biased at a predetera first monostablemultivibrator in one channel producmined level in one channel output;ing erase pulses on an output thereof by triggering of a monostablemultivibrator coupled to the output of said fixed frequency pulses, saidmultivibrator being said astable multivibrator to be triggered therebyand adjustable to vary pulse Width; adjustable to produce brightnesspulses of variable a biasing circuit coupled to the output of said firstwidth on an output thereof in another channel; monostable multivibratorto bias said erase pulses an OR gate coupled to the outputs of saidastable toa predetermined level;

and monostable rnultivibrators to pass either pulse a spike generatorcoupled in the other channel to genas said brightness pulse on an outputthereof in leadcrate spike voltages upon being triggered by said ingedge time coincidence with said erase pulse; fixed frequency pulses,said generator being adjusta brightness amplifier coupled to the outputof said able to vary the spike voltage amplitude;

OR gate to produce an amplified brightness pulse a resistor-capacitornetwork coupled to said spike genon an output thereof; and erator toshape said spike voltage into a sawtooth means in said other channel toproduce said brightness Voltage proportional to spike voltage amplitude;

pulse in a polarity relation opposite to said erase a diferentiatorcoupled to said resistor-capacitor netpulse whereby erase and brightnesspulse are prowork to produce -a differentiated brightness pulse of ducedby adjustably variable duty cycle to control the a width proportional toinput pulse amplitude; persistence and brightness voltages for thedirect view an inverter coupled to the output of said differentiatorstorage tube during erase of stored information. 'E0 invert SaidbfightneSS P11156;

3. Control circuitry for coupling to the backing elecan OR gate coupledto receive said erase and brighttrode and suppressor grid 0f a directview storage tube 35 ness pulses on inputs thereof to pass brightnesspulses having backing and suppressor grid electrodes comprist0 theOutput thereof; and ing: a brightness amplifier coupled to said OR gateouta generator of fixed frequency pulses conducted over put to controlthe amplitude `and bias level of said 'two output channels; brightnesspulses for the direct view storage tube a first monostable multivibratorin one channel having 40 SUPPfeSSOl grid whereby the duty Cycle 0f Saiderase means therein to vary the output pulse width thereand brightnesspulses are varied to control tube 0f produced by the triggering xedfrequency pulses; brightness during erase of voltage information thereabiasing circuit in said one channel coupled to the outin.

put of said first monostable multivibrator to bias References Cited theoutput pulses to produce erase pulses for the backing electrode; UNITEDSTATES PATENTS a second monostable multivibrator in the other channel3,088,048 4/1963 Ogland et al 315-12 having means therein to vary thewidth of each 3,237,188 2/1966 Shaif et al- 340-347 5() ROBERT L.GRIFFIN, Primary Examiner.

R. BLUM, Assistant Examiner.

